Physique > Accueil > Composants nanoélectroniques > FDSOI > Article
Jing Liu
Univ. Grenoble Alpes
Estelle Lauga-Larroze
Univ. Grenoble Alpes
Serge Subias
Univ. Grenoble Alpes
Frédéric Hameau
CEA LETI
Jean-Michel Fournier
Univ. Grenoble Alpes
Carlos Galup
Universidade Federal de Santa Catarina
Brazil
Sylvain Bourdel
Univ. Grenoble Alpes
Publié le 4 février 2019 DOI : 10.21494/ISTE.OP.2019.0327
A gm/ID based methodology is detailed in this paper in order to help the designers to determine the optimum size of a capacitive feedback LNA by considering the design topology, the specifications to reach and the technology characteristics. Thanks to this methodology, the gm/ID is maximized to minimize the power consumption under design constraints which are the voltage gain, the NF and the input inductor (input Q-factor set). To illustrate this methodology, some capacitve feedback LNAs have been designed with different voltage gain requirements in 28nm FDSOI technology for 2.4GHz applications. Based on the initial parameters obtained following the different steps, three LNAs have been designed and simulated. The post-layout simulation results exhibit very good performances in terms of power consumption, linearity IIP3, bandwith BW and noise figure NF for the three given voltage gains (15dB, 18dB and 20dB). The achieved performances are quantified by high values of a well known FoM.
A gm/ID based methodology is detailed in this paper in order to help the designers to determine the optimum size of a capacitive feedback LNA by considering the design topology, the specifications to reach and the technology characteristics. Thanks to this methodology, the gm/ID is maximized to minimize the power consumption under design constraints which are the voltage gain, the NF and the input inductor (input Q-factor set). To illustrate this methodology, some capacitve feedback LNAs have been designed with different voltage gain requirements in 28nm FDSOI technology for 2.4GHz applications. Based on the initial parameters obtained following the different steps, three LNAs have been designed and simulated. The post-layout simulation results exhibit very good performances in terms of power consumption, linearity IIP3, bandwith BW and noise figure NF for the three given voltage gains (15dB, 18dB and 20dB). The achieved performances are quantified by high values of a well known FoM.