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Vol 2 - FDSOI

Nanoelectronic Devices

List of Articles

Analogue and RF performances of Fully Depleted SOI MOSFET

Performance of RF integrated circuit (IC) is directly linked to the analogue and high frequency characteristics of the transistors, the quality of the back-end of line process as well as the electromagnetic properties of the substrate. Thanks to the introduction of the trap-rich high-resistivity Silicon-on-Insulator (SOI) substrate on the market, the ICs requirements in term of linearity are fulfilled. Today Partially Depleted (PD) SOI MOSFET is the mainstream technology for RF SOI systems. Future generations of mobile communication systems will require transistors with better high frequency performance operating at lower power consumption and in the millimeter-waves range. Fully Depleted (FD) SOI MOSFET is a quite promising candidate for the development of these future wireless communication systems. Most of the reported data on FD SOI concern their digital performance. In this paper, their analogue/RF behaviour is described and compared with bulk MOSFETs. Self-heating issue, non-linear behaviour as well as high frequency performance at cryogenic temperature for FD SOI MOSFET are discussed. Finally, a brief summary of the published RF and millimeter-waves ICs based on FD SOI technology is presented.

Analytical expression of top surface charge sensitivity in fully depleted semiconductor on insulator MOS transistor

An analytical expression of free top surface charge sensitivity in FDSOI MOS structure has been established for weak inversion region and validated by TCAD numerical simulation. The influence of various FDSOI stack parameters has been analyzed. The impact of the interface trap density has been particularly emphasized, leading to a strong undesired degradation of sensitivity. This indicates that top surface passivation is a key issue for efficient charge sensing. These expressions of top surface charge sensitivity and associated threshold voltage shift should be very useful for sensor design and electrical characterization purpose.

gm/ID based methodology for capacitive feedback LNA design

A gm/ID based methodology is detailed in this paper in order to help the designers to determine the optimum size of a capacitive feedback LNA by considering the design topology, the specifications to reach and the technology characteristics. Thanks to this methodology, the gm/ID is maximized to minimize the power consumption under design constraints which are the voltage gain, the NF and the input inductor (input Q-factor set). To illustrate this methodology, some capacitve feedback LNAs have been designed with different voltage gain requirements in 28nm FDSOI technology for 2.4GHz applications. Based on the initial parameters obtained following the different steps, three LNAs have been designed and simulated. The post-layout simulation results exhibit very good performances in terms of power consumption, linearity IIP3, bandwith BW and noise figure NF for the three given voltage gains (15dB, 18dB and 20dB). The achieved performances are quantified by high values of a well known FoM.

22FDX® Technologies for Ultra-Low Power IoT, RF and mmWave Applications

In this work we revisited the 22nm FDSOI technology for lowest power IoT, RF and mmWave applications. Ultra-low leakage and power devices are described, as part of the 22FDX® portfolio. Transistors performance is presented. N-FET (p-FET) drive current of 910μA/μm (856μA/μm) at 0.8V and 100pA/μm Ioff are reported fulfilling the requirements for ultra-low power and leakage design space. Excellent low noise is shown due to the suppressed RDF coming from the un-doped silicon channel. Superior fT and fmax have been measured on CMOS and LDMOS devices. 347GHz n-FET fT and 371GHz fmax were achieved on thin oxide CMOS devices. Simple PA circuit results are reported to highlight the benefit of 22FDX® technology for RF and mmWave applications. In conclusion, an outlook of the scalability as well as novel process integrations are discussed.

Electrical characterization of advanced FDSOI CMOS devices

FDSOI technologies are very promising candidates for future CMOS circuits as they feature low variability, improved short channel effect and good transport characteristics. In this paper, we review the main electrical techniques and methodologies used to characterize the important MOS device parameters. First, the capacitance-voltage measurements are considered for the vertical stack characterization of FDSOI structures with HK/MG gate, ultra thin film channel, thin box oxide and back plane substrate. Then, the MOSFET parameter extraction methods are illustrated, as well as the transport and mobility assessment using various techniques (I-V, magneto-transport). Finally, the methodology to study the local variability of the electrical characteristics is also discussed.

Other issues :


Volume 18- 1

Tunnel FETs


Volume 19- 2



Volume 20- 3

Issue 1