TY  - Type of reference 
TI  - Impact of Non-idealities on the Performance of InAs/(In)GaAsSb/GaSb Tunnel FETs 
AU  - S. Sant 
AU  - E. Memisevic 
AU  - L.-E. Wernersson 
AU  - A. Schenk 
AB  - Measured InGaAsSb/InAs nanowire TFETs showing both, sub-60mV/dec slope and high ON-current, are simulated using calibrated TCAD. The focus is laid on the impact of non-idealities, such as hetero-interface traps, oxide-interface traps, and bulk traps on device characteristics. Simulated temperature-dependent transfer curves are in good agreement with the measured data which validates the simulation set-up. It is found that trap-assisted tunneling involving bulk traps adjacent to the hetero-junction is primarily responsible for the degradation of the swing. Due to the small diameter of the nanowire, trap-assisted tunneling is inhibited at the InAs/oxide interface. Still, oxide interface traps reduce the electrostatic coupling between gate and channel, which further increases the swing. The TCAD analysis correctly predicts the negative transconductance observed at high gate bias. If the same simulation set-up is used to study the effect of gate alignment, a significant improvement of both ON-current and swing is found. 
DO  - 10.21494/ISTE.OP.2018.0221 
JF  - Nanoelectronic Devices 
KW  - III-V semiconductors,  Tunnel FETs,  trap-assisted tunneling,  negative transconductance, III-V semiconductors,  Tunnel FETs,  trap-assisted tunneling,  negative transconductance,  
L1  - http://openscience.fr/IMG/pdf/iste_componano18v1n5.pdf 
LA  - en 
PB  - ISTE OpenScience 
DA  - 2018/02/16 
SN  - 2516-3914 
TT  - Impact des non-idéalités sur les performances des FET Tunnel InAs / (In)GaAsSb / GaSb  
UR  - http://openscience.fr/Impact-of-Non-idealities-on-the-Performance-of-InAs-In-GaAsSb-GaSb-Tunnel-FETs 
IS  - Tunnel FETs 
VL  - 1 
ER  -