Physique > Accueil > Composants nanoélectroniques > Numéro
Les performances des circuits intégrés RF sont directement liées aux caractéristiques analogiques et haute fréquence des transistors, à la qualité des interconnexions métalliques ainsi qu’aux propriétés électromagnétiques du substrat. Grâce à l’introduction sur le marché du substrat SOI (Silicium sur Isolant) à haute résistivité et riche en pièges, les spécifications des circuits intégrés en termes de linéarité sont satisfaites. Aujourd’hui, le MOSFET SOI partiellement déserté (PD) est la technologie principale des systèmes SOI RF. Les futures générations de systèmes de communication mobiles nécessiteront des transistors offrant de meilleures performances haute fréquence, fonctionnant à une consommation d’énergie inférieure et dans la plage des ondes millimétriques. Le MOSFET SOI entièrement déserté (FD) est un candidat très prometteur pour le développement de ces futurs systèmes de communication sans fil. La plupart des données rapportées sur FD SOI concernent leurs performances digitales. Dans cet article, leur comportement analogique / RF est décrit et comparé aux MOSFETs en silicium massif. Les problèmes d’auto-échauffement, le comportement non linéaire ainsi que les performances haute fréquence aux températures cryogéniques des MOSFETs FD SOI sont discutés. Enfin, un bref résumé des IC publiés aux ondes RF et millimétriques basés sur la technologie FD SOI est présenté.
An analytical expression of free top surface charge sensitivity in FDSOI MOS structure has been established for weak inversion region and validated by TCAD numerical simulation. The influence of various FDSOI stack parameters has been analyzed. The impact of the interface trap density has been particularly emphasized, leading to a strong undesired degradation of sensitivity. This indicates that top surface passivation is a key issue for efficient charge sensing. These expressions of top surface charge sensitivity and associated threshold voltage shift should be very useful for sensor design and electrical characterization purpose.
A gm/ID based methodology is detailed in this paper in order to help the designers to determine the optimum size of a capacitive feedback LNA by considering the design topology, the specifications to reach and the technology characteristics. Thanks to this methodology, the gm/ID is maximized to minimize the power consumption under design constraints which are the voltage gain, the NF and the input inductor (input Q-factor set). To illustrate this methodology, some capacitve feedback LNAs have been designed with different voltage gain requirements in 28nm FDSOI technology for 2.4GHz applications. Based on the initial parameters obtained following the different steps, three LNAs have been designed and simulated. The post-layout simulation results exhibit very good performances in terms of power consumption, linearity IIP3, bandwith BW and noise figure NF for the three given voltage gains (15dB, 18dB and 20dB). The achieved performances are quantified by high values of a well known FoM.
In this work we revisited the 22nm FDSOI technology for lowest power IoT, RF and mmWave applications. Ultra-low leakage and power devices are described, as part of the 22FDX® portfolio. Transistors performance is presented. N-FET (p-FET) drive current of 910μA/μm (856μA/μm) at 0.8V and 100pA/μm Ioff are reported fulfilling the requirements for ultra-low power and leakage design space. Excellent low noise is shown due to the suppressed RDF coming from the un-doped silicon channel. Superior fT and fmax have been measured on CMOS and LDMOS devices. 347GHz n-FET fT and 371GHz fmax were achieved on thin oxide CMOS devices. Simple PA circuit results are reported to highlight the benefit of 22FDX® technology for RF and mmWave applications. In conclusion, an outlook of the scalability as well as novel process integrations are discussed.
FDSOI technologies are very promising candidates for future CMOS circuits as they feature low variability, improved short channel effect and good transport characteristics. In this paper, we review the main electrical techniques and methodologies used to characterize the important MOS device parameters. First, the capacitance-voltage measurements are considered for the vertical stack characterization of FDSOI structures with HK/MG gate, ultra thin film channel, thin box oxide and back plane substrate. Then, the MOSFET parameter extraction methods are illustrated, as well as the transport and mobility assessment using various techniques (I-V, magneto-transport). Finally, the methodology to study the local variability of the electrical characteristics is also discussed.
