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Composants nanoélectroniques

Nanoelectronic Devices

CompoNano - ISSN 2516-3914 - © ISTE Ltd

Objectifs de la revue

Aims and scope

Composants nanoélectroniques couvre les sujets suivants :

– Composants FD-SOI
– Composants Multi-Grilles sur substrats de Si massif ou sur isolant
– Composants à base de structures 1D
– Composants à base de structures 2D
– Composants Multi-Canaux
– Composants Small-Slope-Switches
– Composants très faible consommation
– Matériaux alternatifs pour les canaux des composants nanoélectroniques
– Conception, technologie, intégration, modélisation, simulation numérique
et caractérisation des composants nanoélectroniques
– Conception de circuits basés sur les composants nanoélectroniques
– Mémoires Non-Volatiles, DRAM, SRAM basées sur un stockage de charges
ou une variation de résistance (PCRAM, RRAM, MRAM)

Nanoelectronic Devices covers the following subjects :


– FD-SOI Devices
– Multi-Gate devices on bulk or insulator substrates
– 1D Devices (Nanowires, Carbon Nanotubes, etc.)
– 2D channel Devices
– Multi-channel Devices
– Small Slope Switches Devices (Tunnel FET, FeFET, NEMS, etc.)
– Ultra low power Devices
– Nanodevices with alternative channel materials
– Design, technology, integration, modelling, numerical simulation
of Nanoelectronic devices
– Circuit design based on nanoelectronic devices
– Charge-based and non-charge based (PCRAM, RRAM, MRAM)
DRAM, SRAM, and Non-Volatile Memories

Numéros parus


Volume 18- 1

Tunnel FETs


Volume 19- 2


Derniers articles parus

Expression analytique de la sensibilité de la charge de surface avant pour les transistors MOS semiconducteur sur isolant complètement déplétés

An analytical expression of free top surface charge sensitivity in FDSOI MOS structure has been established for weak inversion region and validated by TCAD numerical simulation. The influence of various FDSOI stack (...)

Méthodologie basée sur gm / ID pour la conception de LNA à retour capacitifs

A gm/ID based methodology is detailed in this paper in order to help the designers to determine the optimum size of a capacitive feedback LNA by considering the design topology, the specifications to reach and the (...)

Technologies 22FDX® pour les Applications très basse puissance IoT, RF et Ondes Millimétriques

In this work we revisited the 22nm FDSOI technology for lowest power IoT, RF and mmWave applications. Ultra-low leakage and power devices are described, as part of the 22FDX® portfolio. Transistors performance is presented. (...)

Caractérisation électrique des Dispositifs CMOS FDSOI avancés

FDSOI technologies are very promising candidates for future CMOS circuits as they feature low variability, improved short channel effect and good transport characteristics. In this paper, we review the main electrical (...)

FET à effet Tunnel pour les Nanocomposants ultra basse puissance

Future ICs are facing dramatic challenges in performance as well as static and dynamic power consumption, which could be overcome using disruptive concepts, device architectures, technologies and materials. Promising (...)

Effets limitant la performance des FET Tunnel

In this paper a two-dimensional analytical Tunnel-FET model is revised. It is used to evaluate performance enhancing measures for the TFET regarding device geometry and physical effects. The usage of hetero-junctions is (...)

Impact des non-idéalités sur les performances des FET Tunnel InAs / (In)GaAsSb / GaSb

Measured InGaAsSb/InAs nanowire TFETs showing both, sub-60mV/dec slope and high ON-current, are simulated using calibrated TCAD. The focus is laid on the impact of non-idealities, such as hetero-interface traps, (...)

Simulation de transistors à effet de champ tunnel à base de matériaux 2D : architectures planaires vs. verticales

Thanks to their thinness, self-passivated surface and large variety, two-dimensional materials have attracted much interest for their possible application in nanoelectronics. In particular, semiconducting transition metal (...)

Transistors à effet de champ SiGe à effet tunnel linéaire

In this paper we report on our progress with SiGe gate-normal / line tunneling FETs, highlighting recent advancements by the example of three transistor concepts. We demonstrate the unique characteristics shared by these (...)

Comité de rédaction

Rédacteur en chef

CNRS-Grenoble INP-Minatec

Membres du comité

SOITEC, Grenoble

CEA-LETI, Grenoble

Olivier THOMAS
CEA-LETI, Grenoble

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